Senior Engineer – FPGA & ASIC System Architecture

About the role

SES is looking for a Senior Engineer to lead the architecture and delivery of advanced digital payload and radio‑unit solutions for its next‑generation MEO satellite programme, meoSphere. The role combines system‑level design, hardware bring‑up and technical leadership across multiple programmes.

Key responsibilities

• Define and own FPGA and ASIC system architectures for RF and digital communication subsystems across several satellite programmes.
• Translate system‑level requirements into detailed specifications, including clock/reset strategies, interface definitions and low‑level register maps.
• Architect advanced DSP chains such as beamforming, digital front‑end, up/down conversion and crest‑factor reduction.
• Lead high‑speed data‑interface design (Ethernet, eCPRI, RF‑over‑Ethernet) and ensure compliance with 3GPP 5G NR/FR2 standards.
• Provide technical leadership, mentor RTL teams and drive verification, hardware bring‑up and debugging activities.
• Maintain ASIC and FPGA requirements traceability and contribute to roadmap and risk‑mitigation planning.

Required profile

• Master’s degree or PhD in Electrical Engineering, Telecommunications, Computer Engineering or related field.
• 10+ years of hands‑on experience in FPGA and/or ASIC system design, preferably with AMD/Xilinx RFSoC platforms.
• Fluency in English and eligibility for a “SECRET” security clearance.
• Willingness to work at least 60% onsite in Betzdorf and travel as required for project execution.

Required skills

• AMD/Xilinx RFSoC or comparable FPGA platforms
• ASIC design and architecture
• RF digital signal processing (beamforming, DFE, conversion chains)
• ADC/DAC interfacing and IF signal processing
• Multi‑clock‑domain and high‑speed digital design
• High‑speed interfaces: Ethernet, JESD, eCPRI, RF‑over‑Ethernet
• 3GPP 5G NR / FR2 standards knowledge
• Hardware bring‑up, integration and debugging
• RTL design, verification planning and resource/performance analysis