Senior HDL Designer (SystemVerilog/VHDL)

About the role

Join an international engineering team focused on advanced electronic design for the defense sector. As a Senior HDL Designer you will translate system‑level requirements into high‑quality RTL, develop test benches, and bring FPGA prototypes to production.

Key responsibilities

• Convert system specifications into RTL design documents and test benches using SystemVerilog and/or VHDL.
• Size resources, set performance targets, and select appropriate FPGA devices.
• Synthesize, place, and route FPGA designs on physical prototypes, achieving timing closure.
• Optimize designs for cost, technology constraints, and performance.
• Debug prototypes with logic analyzers, ILAs, and oscilloscopes alongside hardware designers.
• Collaborate with hardware and software engineers throughout system integration.
• Develop FIR/IIR signal‑processing algorithms for RF, video, or other digital signals.

Required profile

• Proven experience integrating FPGA designs into digital and mixed‑signal systems.
• Strong expertise in SystemVerilog (preferred) or VHDL.
• Deep knowledge of digital interface protocols such as AXI, SPI, and PCIe.
• Hands‑on experience with lab instrumentation (logic analyzers, ILAs, oscilloscopes).
• Bachelor’s or Master’s degree in Electronic Engineering or related field.
• Fluent English; French or Ukrainian a plus.

Required skills

• SystemVerilog
• VHDL
• FPGA design and synthesis
• AXI, SPI, PCIe protocols
• Signal‑processing algorithm development (FIR/IIR)
• Git version control
• Logic analyzers, ILAs, oscilloscopes

What we offer

• International community with 110+ nationalities.
• Strong internal training academy with 250+ modules.
• Vibrant workplace events and ESG initiatives.
• Equal‑opportunity environment promoting diversity and inclusion.