Embedded Software Engineer – High‑Speed PCB Design for Spacecraft

About the role

We are seeking an experienced Embedded Software Engineer to lead high‑speed PCB design for spacecraft payload electronics. You will own the design from concept through layout release, ensuring compliance with aerospace standards and seamless integration with mechanical and thermal subsystems.

Key responsibilities

• Own high‑speed PCB design for spacecraft payload electronics, from concept to layout release.
• Define and maintain technical specifications for electronic subsystems and high‑speed interfaces.
• Design PCBs to ECSS and/or IPC Class 3 requirements, including stack‑up definition, controlled impedance routing, and manufacturability constraints.
• Perform signal‑integrity and power‑integrity analysis and simulations (impedance profiles, eye diagrams, return loss, crosstalk, PDN impedance) and translate results into layout constraints.
• Drive component selection for high‑speed designs, qualify COTS/HiRel parts and PCB assemblies.
• Prepare and support electrical test campaigns (functional, performance, EMC, ESD) with test and system teams.
• Assess reliability, failure modes, and safety of components; contribute to design reviews and risk mitigation.
• Troubleshoot and resolve design issues during development, bring‑up, testing, and integration.
• Collaborate closely with mechanical, thermal, and systems engineering for clean module integration.

Required profile

• Master's degree in Electronics Engineering or equivalent professional experience.
• Minimum 5 years of PCB design experience.
• Proven expertise with high‑speed layout practices and standards.
• Strong analytical and problem‑solving skills with a hands‑on bring‑up/debug mindset.

Required skills

• Altium Designer (or equivalent PCB design tool).
• High‑speed PCB design and controlled impedance routing.
• Signal integrity and power integrity analysis and simulation.
• Impedance profiling, eye‑diagram analysis, return‑loss and crosstalk assessment.
• Stack‑up definition, differential pair routing, length matching.
• Parasitic modeling, via/return‑path optimization.
• EMC‑aware layout and compliance with ECSS/IPC Class 3 standards.
• Technical documentation preparation (schematics, layout constraints, engineering reports).