FPGA Engineer

About the role

OQ Technology is seeking an FPGA Engineer to join its payload and radio development team in Luxembourg. The engineer will design, implement, integrate and verify FPGA firmware for satellite payloads and telecommunications applications, working alongside hardware, software, RF and systems engineers.

Key responsibilities

• Architect and code FPGA firmware in VHDL and/or Verilog/SystemVerilog for digital signal processing, high‑speed interfaces and control logic.
• Optimize resource utilisation, timing closure and power efficiency on Xilinx/AMD Zynq, Zynq UltraScale+, Kintex, Virtex and Artix families using Vivado and Vitis.
• Implement DSP algorithms (filtering, modulation/demodulation, FFT, decimation, baseband processing) using RTL or High‑Level Synthesis.
• Develop and verify high‑speed communication interfaces such as AXI4, AXI‑Stream, AXI‑Lite, JESD204B, PCIe, Ethernet, SPI, I²C, UART and DDR4.
• Create testbenches, run functional and regression simulations, and document results against specifications.
• Integrate FPGA logic with embedded processors (ARM Cortex‑A53, Cortex‑R5, MicroBlaze) running Linux, RTOS or bare‑metal environments.

Required profile

• Strong background in FPGA firmware development for space, telecom or related high‑speed digital domains.
• Experience with RTL design, simulation and hardware bring‑up.
• Ability to work in a multidisciplinary team and follow the full development lifecycle.

Required skills

• VHDL, Verilog/SystemVerilog
• Xilinx/AMD Zynq, Zynq UltraScale+, Kintex, Virtex, Artix
• Vivado, Vitis toolchains
• DSP algorithm implementation (filtering, modulation, FFT, decimation)
• AXI4, AXI‑Stream, AXI‑Lite, JESD204B, PCIe, Ethernet, SPI, I²C, UART, DDR4
• Testbench development and functional/regression simulation
• Embedded processors: ARM Cortex‑A53, Cortex‑R5, MicroBlaze
• Linux, RTOS, bare‑metal integration