High-Speed PCB Design Engineer for Space Payloads

About the role

We are seeking a High‑Speed PCB Design Engineer to lead the development of spacecraft payload electronics. You will own the hardware from concept through layout release, working in a zero‑margin environment where precision and reliability are critical.

Key responsibilities

• Lead high‑speed PCB design for payload electronics across the full development lifecycle.
• Define and maintain technical specifications for electronic subsystems and high‑speed interfaces.
• Design to ECSS and IPC Class 3 standards, including stack‑up definition, controlled‑impedance routing, and manufacturability constraints.
• Run signal‑integrity and power‑integrity simulations (impedance profiles, eye diagrams, return loss, crosstalk, PDN impedance) and translate results into layout constraints.
• Select components (COTS and HiRel), qualify parts and PCB assembly processes.
• Prepare and support electrical test campaigns (functional, performance, EMC, ESD) alongside test and systems teams.
• Assess reliability, failure modes, and safety of components and interconnects, contributing to design reviews and risk mitigation.
• Troubleshoot design issues through development, bring‑up, test, and integration to keep the programme on schedule.
• Collaborate with mechanical, thermal, and systems engineers to ensure seamless integration.

Required profile

• Master’s degree in Electronics Engineering or equivalent professional experience.
• At least five years of PCB design experience with a strong high‑speed background.
• Proficiency in Altium Designer (or comparable high‑end PCB tool) and solid knowledge of controlled‑impedance routing, differential pair routing, and parasitic modelling.
• Ability to produce clear technical documentation, including schematics, layout constraints, stack‑up definitions, and engineering reports.
• Hands‑on debug mindset and strong analytical problem‑solving skills.

Required skills

• High‑speed PCB design
• Altium Designer
• Controlled impedance routing
• Microstrip and stripline stack‑up planning
• Differential pair routing and length matching
• Propagation delay management
• Parasitics modelling
• Via and return path optimisation
• Crosstalk minimisation
• EMC‑aware layout practices
• Signal integrity analysis
• Power integrity analysis
• Impedance profiling
• Eye diagram analysis
• Return loss measurement
• PDN impedance analysis
• Component selection (COTS, HiRel)
• ECSS standards compliance
• IPC Class 3 compliance
• Technical documentation (schematics, layout constraints, stack‑up definitions)